The invention relates to a memory configuration including a plurality of resistive ferroelectric memory cells.
Ferroelectric memory configurations, in which the cell plate voltage is fixed at half the supply voltage (Vcc/2) of the memory configuration, are distinguished by fast memory operations. However, in these memory configurations, the problem of a possible loss of the data stored in the storage capacitors arises. Since the cell nodes at the storage capacitors are floating as long as the selection transistors are in the off state or blocking state, and these cell nodes form parasitic pn junctions to the semiconductor substrate, leakage currents, which inevitably occur, cause, via these pn junctions, a decrease in the cell node voltage to ground voltage Vss. At the same time, the other nodes of the ferroelectric storage capacitors remain at the fixed cell plate voltage Vcc/2. As a result, the content of the ferroelectric storage capacitors can be corrupted by reprogramming.
In order to avoid this loss of data, the memory cells are refreshed, in a similar manner to what happens in DRAMs (Dynamic Random Access Memory Cells), before the content of the memory cells is corrupted or destroyed. The refresh is effected as follows: the bit lines of the memory configuration are precharged to half the supply voltage Vcc/2 and the cell nodes, through activation of the word lines, are likewise charged to half the supply voltage Vcc/2, so that 0 V drop across the storage capacitors.
Such a refresh is complicated and requires additional operations which should if possible be avoided.
U.S. Pat. No. 5,121,353 describes a memory configuration having ferroelectric memory cells that operates statically and can dispense with a refresh. For this purpose, however, each storage capacitor must be assigned two selection transistors which each have to be connected to different word lines, which makes this known memory configuration complicated.
It is accordingly an object of the invention to provide a memory configuration which overcomes the above-mentioned disadvantages of the heretofore-known memory configurations of this general type and which has a simple construction and which has resistive ferroelectric memory cells which are each configured in such a way that a leakage current at the cell node can no longer cause reprogramming of the respective memory cells, so that it is possible to dispense with a refresh of the memory cells.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory configuration, including:
a plurality of resistive ferroelectric memory cells, each of the resistive ferroelectric memory cells including a selection transistor and a storage capacitor;
the selection transistor having a given zone of a first conductivity type;
the storage capacitor having a first electrode and a second electrode, the first electrode being supplied with a fixed cell plate voltage, the second electrode being connected to the given zone of the first conductivity type;
a semiconductor substrate of a second conductivity type opposite the first conductivity type;
the selection transistor and the storage capacitor respectively being provided in or on the semiconductor substrate;
a MOS transistor having a source, a drain, and a channel, the source and the drain being supplied with the fixed cell plate voltage, the channel having a channel length extending over at least two of the resistive ferroelectric memory cells;
a resistor; and
the given zone of the first conductivity type being connected, via the resistor, to the channel of the MOS transistor such that the given zone is electrically connected to the first electrode of the storage capacitor via the resistor and the MOS transistor.
In other words, a memory configuration according to the invention includes a plurality of resistive ferroelectric memory cells each including a selection transistor and a storage capacitor, one electrode of which is at a fixed cell plate voltage and the other electrode of which is connected to a zone of the selection transistor, the zone having a first conduction type, the selection transistor and the storage capacitor respectively being provided in and on a semiconductor substrate of a second conduction type, which is opposite to the first conduction type, the zone of the selection transistor which is connected to the storage capaciter is connected via a resistor to the channel of a MOS transistor whose channel length extends over at least two memory cells and to whose drain and source the fixed cell plate voltage is applied, so that the zone connected to the storage capacitor is electrically connected to one electrode of the storage capacitor via the resistor and the MOS transistor.
In the memory configuration according to the invention, the two electrodes of the storage capacitor, that is to say the so-called capacitance nodes, are thus connected to one another via a resistor and a connecting line formed by the MOS transistor. The connecting line formed of the MOS transistor having a long channel length is kept at the cell plate voltage.
The resistor should be dimensioned in such a way that its resistance is significantly less than the value of the reverse resistancexe2x80x94formed by the pn junctionxe2x80x94of the selection transistor between the latter""s drain and source and the semiconductor substrate, wherein the reading and writing operation should only be influenced extremely slightly by this resistor.
This ensures that, on the one hand, the reading and writing operation is virtually undisturbed by the resistor and, on the other hand, the leakage current of the parasitic pn junction to the semiconductor substrate is compensated for by the resistor, so that approximately the cell plate voltage is applied to both capacitance nodes of the ferroelectric storage capacitor. As a result, undesired reprogramming of the storage capacitor can no longer take place, so that it is possible to dispense with a refresh.
Consequently, what is essential about the invention is that that end or node of the resistor which is to be connected to that electrode of the storage capacitor which is at the fixed cell plate voltage is kept at the cell plate voltage via a MOS transistor whose channel length extends over a plurality of memory cells. Thus, by way of example, 20 to 100 memory cells are at the cell plate voltage via the drain and source regions of this MOS transistor via a contact and a line composed of aluminum, for example. Thus according to a preferred feature of the invention, the MOS transistor extends, with the channel, over a given number of the resistive ferroelectric memory cells. In particular, the channel of the MOS transistor extends over 20 to 100 of the resistive ferroelectric memory cells.
There are two embodiment variants for the configuration of the resistor and of the connecting line including the MOS transistor:
In the first variant, the resistor is realized by a suitable doping under the thick oxide next to the selection transistor, one end of this resistor being kept at the cell plate voltage via the MOS transistor having a long channel length and a gate voltage VZ being applied to the MOS transistor, while the cell plate voltage is applied to the drain and source of the MOS transistor. In this case, the gate voltage VZ is set in such a way that the cell plate voltage extends across the entire channel of the MOS transistor. In other words, according to a preferred feature of the invention, the semiconductor substrate has a doped region, the resistance value of the resistor is set by the doped region; and the MOS transistor is controlled by a gate voltage such that the fixed cell plate voltage can be applied entirely across the channel of the MOS transistor.
In the second variant, both the resistor at each memory cell and the feeding of the cell plate voltage are realized via the MOS transistor having a long channel length, the cell plate voltage being applied to the drain and source of the MOS transistorxe2x80x94as in the first variant.
A voltage VS is applied to the gate of the MOS transistor. The voltage is kept constant at a given value, so that either there results for each memory cell a current which corresponds to the conditions mentioned above for the resistor with regard to the value of the reverse resistance of the pn junction and the reading and writing operation and pulls the corresponding end of the resistor (resistance node) to the cell plate voltage. Alternatively, there results for each cell a current which corresponds to the conditions for the resistor and in addition, after each reading and/or writing operation and also in the event of the application and switching-off of the supply voltage for the memory configuration, brings the gate voltage VS to a value, in order that the individual electrodes of the storage capacitor in the respective memory cells are quickly pulled to the cell plate voltage.
The advantage of this last-mentioned method is that the. electrodes of the storage capacitor are immediately brought to the cell plate voltage. In this case, every one of the MOS transistors having a long channel length can be switched; however, it is also possible to switch only those MOS transistors having a long channel length which belong to the respective bit line and are selected by a bit line decoder.
According to a further feature of the invention, the MOS transistor has a gate which is supplied with a given voltage such that a current to each of the resistive ferroelectric memory cells compensates for the leakage current of the parasitic pn junction to the semiconductor substrate.
In the memory configuration according to the invention, unintentional reprogramming caused by the leakage current of the parasitic pn junction to the substrate is precluded, so that a refresh is not necessary. It is possible to use normal word line decoders. Moreover, the capacitance of the word line is not increased. Unintentional reprogramming is likewise precluded when the supply voltage is switched off. No plug is necessary between, for example, an n+-conducting region at the resistor and that electrode of the storage capacitor which is at the fixed cell plate voltage, which lowers the demands on the technology during the fabrication of the memory configuration since an additional contact hole for the plug is not required. This also makes it possible to save space on the semiconductor substrate. In other words, the memory cell area is not enlarged in the memory configuration according to the invention by comparison with a standard cell. Finally, there is also no need for additional technology and process steps in order to realize the memory configuration according to the invention.
According to another feature of the invention, the selection transistor has a selection transistor drain and a selection transistor source; and the drain and the source of the MOS transistor, the selection transistor drain and the selection transistor source have an identical conductivity type.
According to yet another feature of the invention, the selection transistor has a selection transistor drain; and a plug connects the selection transistor drain to the second electrode of the storage capacitor.
According to another feature of the invention, the selection transistor has a selection transistor source; and a plug connects the selection transistor source to a bit line.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory configuration including a plurality of resistive ferroelectric memory cells, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.